1. Field of the Invention
The present invention relates to a method for controlling a delay time of a signal in a semiconductor device, which can freely adjust delay degree of a predetermined signal in a test mode, and more particularly to a method for controlling a delay time of a signal in a semiconductor device, which can set a desired delay degree by means of an external signal, regardless of the number of unit delay devices constituting a delay circuit.
2. Description of the Prior Art
In a general delay circuit, unit delay devices are connected in a row in order to make a desired delay time (i.e. delay degree). Further, in a test mode adjusting the delay degree, the number of unit delay devices, through which a signal inputted in the delay circuit passes, is adjusted by means of a predetermined control signal, so that the total delay degree (time) is adjusted. In this case, the variation of the delay is limited to an integral number times of the unit delay device, and a maximum value of the total delay degree is determined as the total number of the unit delay devices. Accordingly, the minimum and maximum delay degrees are restrictive.
Hereinafter, the prior art will be described with reference to the accompanying drawings.
FIG. 1 is a block diagram of a conventional delay control circuit. Herein, an input signal “in” is delayed by a predetermined time to be outputted to an output terminal, and the delay degree is determined by control signals “tmsel<0:4>”.
As shown in FIG. 1, the delay control circuit includes a test mode delay section (tm_dly) 100 and a test delay section (tstdly) 120. The test delay section 120 delays the input signal “in” by a predetermined time. The test mode delay section 100 receives test signals “tm_reset and tm_pulse” to output the control signals “tmsel<0:4>” determining the delay degree of the test delay section 120. Herein, a “pwrup” is a power-up signal and represents a driving voltage. An “out” signal represents a signal outputted after the input signal “in” is inputted and delayed for a predetermined time.
FIG. 2 is a block diagram of the test mode delay section 100 shown in FIG. 1.
As shown in FIG. 2, in the case in which the power-up signal “pwrup” is enabled to be at a high level and the test mode reset signal “tm_reset” is enabled to be at a high level, when the test mode pulse signal “tm_pulse” is applied in a pulse shape, the test mode delay section 100 generates predetermined output signals “tmsel<0>, tmsel<1>, tmsel<2>, tmsel<3>, and tmsel<4>”. Herein, the signal “tmsel<1>” is a signal in which the signal “tmsel<0>” passes through a shift resistor 200 to be outputted, the signal “tmsel<2>” is a signal in which the signal “tmsel<1>” passes through a shift resistor 220 to be outputted, the signal “tmsel<3>” is a signal in which the signal “tmsel<2>” passes through a shift resistor 240 to be outputted, the signal “tmsel<4>” is a signal in which the signal “tmsel<3>” passes through a shift resistor 260 to be outputted.
Herein, waveforms of signals in the circuit shown in FIG. 2 are shown in FIG. 7.
As shown in FIG. 7, when the power-up signal “pwrup” is applied to a high state and the test mode pulse signal tm_pulse is toggled in a pulse shape, the output signals “tmsel<0>, tmsel<1>, tmsel<2>, tmsel<3>, and tmsel<4>” show waveforms as shown in FIG. 7.
That is, as shown in FIG. 2 and FIG. 7, the output signal “tmsel<0>” is synchronized with a falling edge of the test mode pulse signal tm_pulse to shift from a high state to a low state. The output signal “tmsel<1>” is synchronized with a falling edge of the output signal “tmsel<0>” to shift from a low state to a high state, and is synchronized with a falling edge of the test mode pulse signal tm_pulse to re-shift to a low state. The output signal “tmsel<2>” is synchronized with a falling edge of the output signal “tmsel<1>” to shift from a low state to a high state, and is synchronized with a falling edge of the test mode pulse signal “tm_pulse” to re-shift to a low state. The output signal “tmsel<3>” is synchronized with a falling edge of the output signal “tmsel<2>” to shift from a low state to a high state, and is synchronized with a falling edge of the test mode pulse signal “tm_pulse” to re-shift to a low state. The output signal “tmsel<4>” is synchronized with a falling edge of the output signal “tmsel<3>” to shift from a low state to a high state, and is synchronized with a falling edge of the test mode pulse signal “tm_pulse” to re-shift to a low state. Next, the output signal “tmsel<0>” is synchronized with a falling edge of the output signal “tmsel<4>” to shift from a low state to a high state, and is synchronized with a falling edge of the test mode pulse signal “tm_pulse” to re-shift to a low state. The operation continuously repeats when the test mode pulse signal “tm_pulse” is continuously applied.
FIG. 3 is a block diagram of the test delay section 120 shown in FIG. 1. In a test mode, the test delay section 120 delays an input signal by a predetermined time and outputs the delayed signal to an output terminal “out” in response to the control signals “tmsel<0:4>”.
As shown in FIG. 3, the input signal “in” of the test delay section 120 is applied to the first delay section 300 from among delay sections 300, 320, 340, and 360 connected in series with each other, and is sequentially delayed. Further, a transmission gate 302 is connected to an input terminal of the delay section 300. A transmission gate 322 is connected to an output terminal of the delay section 300 and an input terminal of the delay section 320. A transmission gate 342 is connected to an output terminal of the delay section 320 and an input terminal of the delay section 340. A transmission gate 362 is connected to an output terminal of the delay section 340 and an input terminal of the delay section 360. A transmission gate 382 is connected to an output terminal of the delay section 360. The transmission gates 302, 322, 342, 362, and 382 are respectively turned on/off by signals “tmsel<2>, tmsel<1>, tmsel<0>, tmsel<3>, and tmsel<4>”. Accordingly, when one of the transmission gates is turned on by the signals “tmsel<2>, tmsel<1>, tmsel<0>, tmsel<3>, and tmsel<4>”, the input signal “in” is delayed by a predetermined time and then outputted.
As shown in FIG. 3, in the prior art, the maximum delay time of the input signal “in” has a predetermined limitation. That is, the prior art has a problem in that the maximum delay time of the input signal is inevitably determined depending on a total number of the delay devices.